User manual LAVRY DA924

[. . . ] LAVRY ENGINEERING SHALL NOT BE LIABLE FOR ANY INDIRECT, INCIDENTAL, CONSEQUENTIAL, PUNITIVE, SPECIAL OR EXEMPLARY LOSSES OR DAMAGES, INCLUDING, WITHOUT LIMITATION, DAMAGES TO RECORDINGS, TAPES OR DISKS, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, LOSS OF GOODWILL, COVER, OR OTHER PECUNIARY LOSS, ARISING OUT OF OR RELATING TO THE USE OF THE PRODUCT, OR ARISING FROM BREACH OF WARRANTY OR CONTRACT, NEGLIGENCE, OR ANY OTHER LEGAL THEORY, EVEN IF LAVRY ENGINEERING HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES OR DAMAGES. ANY DAMAGES THAT LAVRY ENGINEERING IS REQUIRED TO PAY FOR ANY PURPOSE WHATSOEVER SHALL NOT EXCEED THE ORIGINAL COST PAID TO LAVRY ENGINEERING FOR THE APPLICABLE PRODUCT. BECAUSE SOME STATES/JURISDICTIONS DO NOT ALLOW THE EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE FOREGOING LIMITATION MAY NOT APPLY TO YOU. Copyright ©2002 by Lavry Engineering, Inc. Acoustic Bit Correction® and Lavry Engineering® are registered trademarks of Lavry Engineering, Inc. [. . . ] The unit finds the first active input and converts digital audio to analog sound (if the INPUT SELECT Search Mode is enabled. The DA924 determines the incoming sample rate for the selected input and displays the incoming frequency (44. 1, 48, 88. 2 or 96KHz). When all inputs are inactive, the unit steps through the input ports continuously as indicated by the input select lamps (if in Search Mode). Most DAC's contains relays for the purpose of muting the output during turn on (allowing the DAC to settle to proper operating conditions). The DA924 contains no relays, in order to avoid signal degradation associated with relay contacts. The unit minimizes "turn-on spikes" by incorporating very slow tracking power supplies for its output stage, thus disabling the drive capability during turn on. The DA924 turn-on spike may be higher then that found in other DAC's but the sound is not compromised. The spike due to power off is comparable to that found in other DAC's. Polarity Inversion The normal polarity is set to pin 2 "+" or "non-inverted. " To invert, press the POLARITY switch. · · · Inverting while in balanced operation exchanges the polarity of the signals on pin 2 and pin 3 of the XLR connector. Inverting while in unbalanced operation impacts signal polarity on pin 2 of the XLR connector. Inverting while in unbalanced operation impacts signal polarity on the IEC center conductor. 8 DA924 Operation Manual PLL Mode and CrystalLockTM Mode The DA924 features a very low jitter PLL Mode that prevents jitter in the input digital audio signal from degrading DA conversion quality. The PLL mode is recommended for operation of the DA924 with inputs of 88. 2 or 96 kHz. The default setting is PLL mode and is indicated by the Sample Frequency indicator slowly blinking. For additional jitter reduction with inputs of 44. 1 or 48 kHz, select the CrystalLockTM Mode. The CrystalLockTM mode is indicated by the Sample Frequency indicator staying constantly illuminated. To enable CrystalLockTM mode, press and hold the POLARITY button for 1. 5 seconds. This mode setting is retained when power is removed. Power and Fusing The DA924 operates at 50 or 60 Hz, and has two line voltage selections, 115 volts and 230 volts. Voltage selection is made in the power input module on the rear panel. Always disconnect the AC power cord before checking the fuses or changing the voltage setting. The fuse holder is red in color, and the voltage setting indication printed on it is in white lettering. This setting is visible through a small "window" in the hinged cover located next to the AC power switch and input connector. To change or check the fuses or change the operating voltage, carefully open the cover by lifting the right edge and pull the red fuse holder straight out of the power input module. [. . . ] The deglitcher circuit is clocked by a pullable crystal oscillator but the control signal for the crystal is freed from having to track down incoming clock variations. The clock oscillator is controlled by a processor driven DAC, and oscillator frequency is changed by tiny amounts (. 1ppm) and not very often (15 seconds or more) in a manner allowing it to track only very long term average drift. Using such an approach with ordinary PLL will cause loss of lock because the slight variations in incoming data rate cause loss of correspondence between the input and the too steady of a clock circuit. The DA924 CrystalLockTM approach, stores enough data in a dedicated memory to guarantee that each clock cycle can find its data. [. . . ]